1. Field of the Invention
The present invention relates to electronic packages, and more particularly, to an electronic package having a reduced size and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. Accordingly, there have been developed various types of flip-chip packaging modules such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip modules (MCM), and 3D IC chip stacking technologies.
FIG. 1 is a schematic cross-sectional view of a conventional 3D chip stacking-type semiconductor package 1. Referring to FIG. 1, a silicon interposer 10 is provided. The silicon interposer 10 has a chip mounting side 10a, an external connection side 10b opposite to the chip mounting side 10a and having a plurality of redistribution layers 101 formed thereon, and a plurality of through silicon vias (TSVs) 100 communicating the chip mounting side 10a and the external connection side 10b. A semiconductor chip 19 having a plurality of electrode pads 190 is disposed on the chip mounting side 10a of the silicon interposer 10 and the electrode pads 190 are electrically connected to the chip mounting side 10a of the silicon interposer 10 through a plurality of solder bumps 102. The electrode pads 190 have a small pitch therebetween. Further, an underfill 192 is formed between the semiconductor chip 19 and the chip mounting side 10a of the silicon interposer 10 for encapsulating the solder bumps 102. Furthermore, an encapsulant 18 is formed on the silicon interposer 10 to encapsulate the semiconductor chip 19. In addition, a packaging substrate 17 having a plurality of bonding pads 170 is disposed on the external connection side 10b of the silicon interposer 10 and the bonding pads 170 are electrically connected to the redistribution layers 101 through a plurality of conductive elements 103 such as bumps. The bonding pads 170 of the packaging substrate 17 have a large pitch therebetween. Also, an underfill 172 is formed to encapsulate the conductive elements 103.
To fabricate the semiconductor package 1, the semiconductor chip 19 is disposed on the silicon interposer 10 first and then the silicon interposer 10 having the semiconductor chip 19 is disposed on the packaging substrate 17 through the conductive elements 103. Subsequently, the encapsulant 18 is formed, thereby obtaining the semiconductor packager 1.
In the conventional semiconductor package 1, the silicon interposer 10 serves as a signal transmission medium between the semiconductor chip 19 and the packaging substrate 17. To achieve a suitable silicon interposer 10, the TSVs 100 must be controlled to have a certain depth to width ratio (100 um/10 um), thus consuming a large amount of time and chemical agent and incurring a high fabrication cost.
Further, the packaging substrate 17 has a core layer containing glass fiber. Consequently, the packaging substrate 17 is quite thick, which hinders miniaturization of the semiconductor package 1.
Furthermore, when the semiconductor chip 19 has features of fine trace width, fine pitch and high I/O count, the area of the silicon interposer 10 and the area of the corresponding packaging substrate 17 must be increased, thereby hindering miniaturization of the semiconductor package 1.
In addition, an electrical test is generally performed after the semiconductor chip 19 is encapsulated by the encapsulant 18. As such, if the redistribution layers 101 fail to function properly, the overall structure cannot be reworked, resulting in a loss of the chip.
Therefore, how to overcome the above-described drawbacks has become critical.